Recent developments in the semiconductor integrated circuits have made a demand for an interconnection replacing the conventional aluminum (Al)-based interconnection. In particular, a resistance-capacitance (RC) delay caused by an interconnection due to the miniaturization of semiconductor integrated circuits has increased relative to that caused by a semiconductor device, particularly a transistor. Further, as interconnection resistance increases in connection with the miniaturization of an interconnection width, studies are being made to replace the Al-based interconnection.
This increase of the interconnection resistance causes a voltage drop of a power line, and increases the density of current flowing through the interconnection, thereby degrading electrical reliability of the semiconductor device. Therefore there is a tendency to replace the Al-based interconnection with a copper (Cu)-based interconnection. Cu has good conductivity and low resistance, and thus is suitable for the interconnection material.
Unlike the Al interconnection, the Cu interconnection is patterned using a damascene process, particularly a dual damascene process where the filling a contact hole and the formation of an interconnection are performed at the same time.
The dual damascene process typically includes a process of etching a trench having a depth from 4000 Å to 5000 Å, a process of filling the trench with Cu using an electrochemical plating (ECP) process, a process of removing Cu overfill using a chemical mechanical polishing (CMP) process.
Hereinafter, a conventional method for forming an interconnection of a semiconductor device will be described with reference to the accompanying drawings.
FIGS. 1A, 1B and 1C are front sectional views illustrating a processes of a conventional method for forming an interconnection of a semiconductor device.
According to the conventional method, as illustrated in FIG. 1A, first, a semiconductor substrate 601 having a transistor (not shown) is deposited with Cu, and is patterned to form a first Cu interconnection 603.
A silicon nitride layer, a silicon oxide layer, or a combination thereof is formed on a top surface of the semiconductor substrate 601 including the first Cu interconnection 603, thereby forming an insulating layer 604. Then, the insulating layer 604 is selectively removed by a dual damascene process, thereby forming a via hole 615 and a trench 614. Then, the formed pattern is baked.
Next, referring to FIG. 1B, a barrier layer 606 is formed on inner walls of the via hole 615 and the trench 614 to a thin thickness. A Cu seed layer 602 is deposited on the barrier layer 606. The Cu seed layer is required to perform an ECP process of Cu used for gap-filling Cu in the damascene process.
During the ECP process, the Cu seed layer 602 continues to be rapidly grown, thereby overfilling the via hole 615 and the trench 614 with a Cu layer 605.
Finally, after the Cu deposition is completed by the ECP process, as illustrated in FIG. IC, a CMP process is performed on a top surface of the substrate using a top surface of the insulating layer 604 as an end point. Thereby, a Cu plug 605a and a second Cu interconnection 605b are simultaneously formed in the via hole 615 and the trench 614.
However, the conventional method for forming an interconnection of a semiconductor device has the following disadvantages.
The Al interconnection has been recently replaced by the Cu interconnection. This improves electro-migration (EM) and stress migration (SM), and is favorable from the viewpoint of RC delay and process simplification. However, because Cu a has weak hardness, the CMP process causes scratch, dishing and erosion.
In particular, it is necessary to control surface scratch of the Cu interconnection caused by the CMP process, because the surface scratch has a possibility to cause contact failure when the Cu interconnection is in contact with an upper layer thereof.
A Cu—Al alloy can be used instead of soft, pure Cu to increase the hardness, so that the scratch, dishing and erosion can be reduced in the CMP process, and the EM and SM characteristics of a gradually narrowed interconnection can be improved.
However, it is difficult to deposit Al using the ECP process used to deposit Cu. As such, Al is deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD). For this reason, the conventional method has difficulty in using the Cu—Al alloy.